Turn in all of these files into one compressed file, named like (student1 name)_(student2 name)_final.zip, or (student name)_final.zip if you are working alone, and send to the TA's email address.

[ Part A : Min Delay ]

1. Your final report.
2. Verilog code.
3. ModelSim simulations.
4. Area (.flow file) and timing reports (.sta file).

[ Part B : Min Delay * Area ]

1. Your final report.
2. Verilog code.
3. ModelSim simulations.
4. Area (.flow file) and timing reports (.sta file).

For the ModelSim simulations, please provide simulation results for BOTH SHA1_hash_testbench_v6.v and SHA1_hash_testbench_511.v.

However, in your final report, use the area and timing results from ONLY SHA1_hash_testbench_v6.v summarize the design.

If you are using one design for both Part A and Part B, then just submit one set of summary, Verilog code, ModelSim results, and area and timing reports.  Most groups will submit just one design.

Depending if you are enrolled in Section A00, B00, or C00, you should send your compressed file to one following respective email addresses:

ece111a00@gmail.com or
ece111b00@gmail.com or
ece111c00@gmail.com

If you and your partner are in different sections, then email your compressed file to the email address that corresponds to the section of the student who is submitting.

The "Subject" line of your email should say "SHA1 project".