Turn in all of these files into one compressed file, named like (student1 name)_(student2 name)_project1.zip, or (student name)_project1.zip if you are working alone.

1. Copy of your Verilog HDL source code for the fibonacci_calculator module.

2. Copy of the ModelSim simulation results. Please check FAQs on how to save
your modelsim transcript.

3. Copy of the fibonacci_calculator.flow (RPT file) with area numbers and
fibonacci_calculator.sta (RPT file) with fmax summary generated using Quartus.
These files are generated in the project directory. You can also send in
screenshots from the GUI for area and fmax instead of the files.

4. Any document you want to describe your design. (Not Necessary)

Depending if you are enrolled in Section A00, B00, or C00, you should send your compressed file to one following respective email addresses:

ece111a00@gmail.com or
ece111b00@gmail.com or
ece111c00@gmail.com

If you and your partner are in different sections, then email your compressed file to the email address that corresponds to the section of the student who is submitting.

The "Subject" line of your email should say "Fibonacci project".