Turn in all of these files into one compressed file, named like (student1 name)_(student2 name)_project2.zip, or (student name)_project2.zip if you are working alone.

[ Part A ]

1. Summary page with area, #cycles, clock period and total = area * cycles * clock period.
   Use #cycles from rle_testbench.v.
2. Verilog code.
3. ModelSim transcript and Waveforms.
   Provide transcript and waveforms for both rle_testbench.v and rle_testbench2.v to show
   your design works for both testbenches.
4. Area (.flow file) and timing reports (.sta file).

[ Part B ]

1. Summary page with area, #cycles, clock period and total = area * cycles * clock period.
   Use #cycles from rle_testbench.v.
2. Verilog code.
3. ModelSim transcript and Waveforms.
   Provide transcript and waveforms for both rle_testbench.v and rle_testbench2.v to show
   your design works for both testbenches.
4. Area (.flow file) and timing reports (.sta file).

If you are using one design for both Part A and Part B, then just submit one set of summary, Verilog code, ModelSim results, and area and timing reports.  Most groups will submit just one design.

Depending if you are enrolled in Section A00, B00, or C00, you should send your compressed file to one following respective email addresses:

ece111a00@gmail.com or
ece111b00@gmail.com or
ece111c00@gmail.com

If you and your partner are in different sections, then email your compressed file to the email address that corresponds to the section of the student who is submitting.

The "Subject" line of your email should say "RLE project".