module function_call_example_testbench(); reg clk; reg nreset; reg start; integer k; integer i; wire [31:0] retvalue; wire done; function_call_example FFF ( .clk (clk), .nreset (nreset), .start (start), .retvalue (retvalue), .done (done) ); // CLOCK GENERATOR always begin #10; clk = 1'b1; #10 clk = 1'b0; end // MAIN TESTBENCH initial begin // RESET @(posedge clk) nreset = 0; for (k = 0; k < 2; k = k + 1) @(posedge clk); nreset = 1; for (k = 0; k < 2; k = k + 1) @(posedge clk); start = 1'b1; for (k = 0; k < 2; k = k + 1) @(posedge clk); start = 1'b0; wait (done == 1); // DISPLAY RESULT $display("retvalue = %d\n", retvalue); $finish; end endmodule