Project 2 Description
The goal of this project is to design the RLE (Run-Length Encoding) Co-Processor, a HW block that performs a simple lossless data compression algorithm.
1. Objectives:
Design 1: A design that is minimized for delay.
Design 2: A design that is minimized for area*delay product.
Report results as specified in Deliverables
2. Specification:
To understand the RLE algorithm that must be implemented, go over:
This Verilog Module Interface (*****)
contains the RLE Co-processor declaration and explanation of each port:
3. Testbench:
Use this testbench rle_testbench.v
(*****)
and plaintext.dat (*****) file used by the testbench
to verify your design.
This testbench will be used to determine the number of cycles for your delay metric.
Your design must work with this testbench.
In addition, your design must also work with a second testbench called
rle_testbench2.v
(*****) and
plaintextLong.dat
(*****).
For this test case, the compressed text will actually be longer than the original text.
You need to show that your design works for this test case as well, but the first testbench
rle_testbench.v
will be used to compute the delay performance.
For the testbench rle_testbench.v,
the compressed text outputs should be the following.
For the testbench rle_testbench2.v,
the compressed text outputs should be the following.
This is the timing diagram (*****) for reading and writing to the DPSRAM. It is a conservative timing model; however please use this in order to ensure correctness of the design (in the presence of, say, clock skew etc).
Part A: Minimize Delay
- State machine diagram
- Verilog code for the Co-processor
- ModelSim scripts and traces. Illustrate clearly that your
design passes the testbench.
- Results of synthesis: (a) Synthesis script that you used (b) Area, timing
and resource reports. (c) Include warnings (if any).
- Area occupied by the design
- Performance report: Measure time taken by your design to encrypt the
data provided by the testbench.
- Delay (ns) = no. of clock cycles (measured from simulation) * Clock Cycle Time (ns, obtained from synthesis)
- Report Area*Delay value
Part B: Minimize Area*Delay Product
- State machine diagram (if different from Part A)
- Verilog code for the Co-processor (if different from Part A)
- ModelSim scripts and traces. Illustrate clearly that your design passes the testbench.
- Results of synthesis: (a) Synthesis script that you used (b) Area, timing
and resource reports. (c) Include warnings (if any).
- Performance report: Measure time taken by your design to encrypt the
data provided by the testbench.
- Delay (ns) = no. of clock cycles (measured from simulation) * Clock Cycle Time (ns, obtained from synthesis)
- Report Area*Delay value