// Verilog behavioral description of a 4-bit adder module p4ba_alt (A, B, carry_in, sum, carry_out); input [3:0] A; input [3:0] B; input carry_in; output [3:0] sum; output carry_out; reg [3:0] sum; // Declare as type reg since assigned to in the always block reg carry_out; // even though they are "wires" reg [4:0] carry; integer i; always@(*) // can just use "*" instead of specifying list of input signals begin carry[0] = carry_in; for (i=0;i<=3; i=i+1) begin sum[i] = A[i] ^ B[i] ^ carry[i]; carry[i+1] = A[i] & B[i] | A[i] & carry[i] | B[i] & carry[i]; end carry_out = carry[4]; end endmodule