module test2 (reset_n, clk, op, x, dataout); input reset_n; input clk; input op; input [3:0] x; output [3:0] dataout; reg [3:0] y; reg [3:0] z; reg [3:0] dataout; always @ (posedge clk or negedge reset_n) begin if (!reset_n) y <= 4'b0000; else if (op) y <= y + x; else y <= y - x; end always @ (posedge clk or negedge reset_n) if (!reset_n) begin dataout <= 4'b0000; z <= 4'b0000; end else begin z <= y + 1; dataout <= dataout + z; end endmodule