ECE 111 Project 1

Prerequisite

Before you start this project, you should complete tutorial 1.

Project:

Project1 (Project description slides from class)
You are to design using Verilog a controller/datapath that accepts as input a number n on the port input_s, and a clock to drive the controller FSM, and outputs fibo_out, the nth Fibonacci number, some number of clocks later. 

The nth Fibonacci number is the sum of the (n-1)th and (n-2)th Fibonacci number, and the first two numbers in the sequence are F(0) = 0 and F(1) = 1. So the Fibonacci sequence is:

A reset_n signal is necessary to initialize the first two numbers of the sequence to 1 and 1 when reset_n is low.  Your reset using the signal reset_n can be asynchronous or synchronous.  Your design should accept the input value of n on the port input_s when a start signal called begin_fibo is high and reset_n is high.  After begin_fibo transitions from low to high, the design does not require any more inputs other than the clock clk.  Note that your design should be able to process next fibonacci number just by toggling begin_fibo without having to reset the design for each input corresponding to the value of input_s .The output consists of the nth Fibonacci number on the port fibo_out and a done signal of 1 indicates that the output is valid.  When the done signal is 0, then fibo_out can be anything. 

The 23rd Fibonacci number F(23) is 28,657 (6ff1 in hex), which is the largest number you are required to generate.  So the input is 5 bits wide (to accomodate the number 23), while the output is 16 bits wide (to accommodate 28,657). A list of the first 24 Fibonacci numbers is provided for you. 

 Note:Your fibonacci calculator must calculate the nth fibonacci number.   Using a ROM with stored fibonacci numbers is not permitted.

Synthesis note: The loop limit for a for loop or a while loop cannot be variable.  The loop limit must be constant.

Synthesis note:While in general, functions are synthesizable, recursive functions are not.

You should use this module declaration:

                     module fibonacci_calculator (input_s, reset_n, begin_fibo, clk, done, fibo_out) ;
                         input  [4:0] input_s ;
                         input  reset_n ;
                         input  begin_fibo ;
                         input  clk ;
                         output done ;
                         output [15:0] fibo_out ;  
                     endmodule

If you use state machine design style 1, no registers will be synthesized in the combinational (unclocked) always block.  You will need to instantiate the needed registers to hold the n-1 and n-2 fibonacci number to be included with your state machine in your fibonacci module.  To use a single process (always block) to do the algorithm and synthesize the needed registers, you can use state machine design style 4, where signals assigned to in the clocked process are synthesized as registers.  You can code the datapath operations in the state machine, which is called the functional rtl design style as described in functional RTL section of tutorial 1. An example is functional.rtl.v,

Signals, unless optimized out by the synthesis tool, that are assigned to in an unclocked always block, will be synthesized as wires if no memory is inferred or as latches if memory is inferred.  To avoid unwanted latches from the use of unclocked always blocks, signals assigned to in the unclocked process should be assigned a value for each branch in an if or case statement to avoid inferring memory.  Signals, unless optimized out by the synthesis too, that are assigned to in a clocked always block, will be synthesized as registers.