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Icarus Tutorial Page

You can download the Icarus Verilog simulator for Windows at http://bleyer.org/icarus/.

Please note that Icarus is just a simulator -- it does not care if your design is synthesizable. You have to run your design through Quartus to know if it is synthesizable.

During the installation process of Icarus, it will ask you if you want to add the executables to the Windows PATH environment. Leave the checkbox checked (which is the default). This way, you can execute the Icarus executables from a command Windows.

Once installed, there are two commands that you are going to use: iverilog and vvp. iverilog is used to compile your Verilog files, including the testbench, into an executable. vvp is used to run the executable.

Here is a quick explanation page on how to use these commands.

Suppose we have a fibonacci design called fibo3.v and a testbench tb_fibonacci_calculator.v. See the following screenshot:

Notice that we use the command "finish" to end vvp.

For the next example, suppose we have a 4-bit adder called h4ba.v, which instantiates a 1-bit adder called full_adder.v, and a testbench tb_h4ba.v. See the following screenshot:

Notice that you have to include all Verilog files that are used in your design.