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Class Schedule (subject to change)
| Week | Date | Topic | Due |
| 1 | 01/04 | Introduction. Verilog examples, including full_adder.v, h4ba.v, a4ba.v, add4.v, test5.v, p4ba.v, p4ba_alt.v, and add_sub.v. More examples can be found here. Quartus II and ModelSim Tutorials. |
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| 01/06 | RTL Verilog examples, which includes test6.v, test7.v, test1.v, test2.v, test3.v, test4.v, and rtl_example.v. | ||
| 01/08 |
More examples,
which includes
full_adder_alt.v,
p4ba_alt2.v, and
test1_alt.v. Fibonacci project. |
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| 2 | 01/11 |
Another example: p4ba_alt3.v. RLE project |
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| 01/13 | RLE project discussion | ||
| 01/15 | RLE project discussion | ||
| 3 | 01/18 | Martin Luther King, Jr. Holiday | |
| 01/20 | Class | ||
| 01/22 | Class | Fibonacci project | |
| 4 | 01/25 | Class | |
| 01/27 |
Inferred Latch Problem, and examples:
latch_case_problem.v and
latch_if_problem.v. Example Fibonacci Implementations: fibo0.v, fibo3.v, and fibo5.v. RLE project discussion |
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| 01/29 | Class | ||
| 5 | 02/01 | Class | |
| 02/03 | SHA-1 final project | ||
| 02/05 | Class | ||
| 6 | 02/08 | Class | |
| 02/10 | Repeat of SHA-1 project presentation | RLE project (due date EXTENDED to 11:59pm PST Sun 2/14) | |
| 02/12 | Class | ||
| 7 | 02/15 | President's Day Holiday | |
| 02/17 | Loop Pipelining. The corresponding Verilog examples: example_pipe.v and example_nonpipe.v. | ||
| 02/19 | Class | ||
| 8 | 02/22 | Class | |
| 02/24 | Looping Unfolding. Two related papers: IEICE-2009.pdf UCLA-2006.pdf. | ||
| 02/26 | Class | ||
| 9 | 02/29 | Class | |
| 03/02 | ABET final report requirements discussion. Here is the template for your final report. | ||
| 03/04 | Class | ||
| 10 | 03/07 | Class | |
| 03/09 | SHA-2 | ||
| 03/11 | Class | ||
| 11 | 03/16 | Final project due date | Final SHA-1 Project (due 11:59pm PST Wed 3/16) |