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Class Information

• Lectures:
  • Section A00: MWF 11:00am-11:50am, WLH 2204
    
  • Section B00: MWF 12:00pm-12:50pm, WLH 2204
    
  • Section C00: MWF 10:00am-10:50am, EBU1 2315
    
• Discussion: No discussion sections

Instructor

• Prof. Bill Lin, Atkinson Hall 4310
• Office hours: W 9-10am
  
• Email: [email protected]

Teaching Assistants

• Section A00:
  • Yang Song
    Email: [email protected]
    Office hours: TuTh 12:30-3pm, EBU1-2315
    
  • Ping Yin
    Email: [email protected]
    Office hours: TuTh 1-3:30pm, EBU1-2315
    
• Section B00:
  • Sidharth Kodaikkal Vijayan
    Email: [email protected]
    Office hours: M 5-8pm, W 2-4pm, EBU1-2315
    
  • Pranav Marakani
    Email: [email protected]
    Office hours: M 5-7pm, F 3:30-6:30pm, EBU1-2315
    
• Section C00:
  • Shalini Kedlaya
    Email: [email protected]
    Office hours: M 3-5:30pm, F 4-6.30pm, EBU1-2315
    
  • Praneeth Sanapathi
    Email: [email protected]
    Office hours: M 1:30-5pm, W 1:30-3pm, EBU1-2315
    
• Note: You may get help from any of the 6 TAs during their office hours.

Announcements

• 03-23: For the SHA1 project, the top designs for Best Delay are:
  1. Samuel Lois Bauza & Michael Kenji Petrucci:
     • #ALUTs = 1319, #Registers = 1508, Area = 2827
     • Clock frequency = 186.15 MHz, Clock cycles = 146
     • Delay = 784.31 ns, Area*Delay = 2.217 x 10^-3
  2. Jinzhe Zhang:
     • #ALUTs = 594, #Registers = 968, Area = 1562
     • Clock frequency = 321.23 MHz, Clock cycles = 252
     • Delay = 784.48 ns, Area*Delay = 1.225 x 10^-3
  3. Kevin Chihheng Pan & Brandon Tyler Ustaris:
     • #ALUTs = 559, #Registers = 1007, Area = 1566
     • Clock frequency = 325.10 MHz, Clock cycles = 258
     • Delay = 793.60 ns, Area*Delay = 1.243 x 10^-3
  The top designs for Best Area*Delay are:
  1. Jinzhe Zhang:
     • #ALUTs = 594, #Registers = 968, Area = 1562
     • Clock frequency = 321.23 MHz, Clock cycles = 252
     • Delay = 784.48 ns, Area*Delay = 1.225 x 10^-3
  2. Kevin Chihheng Pan & Brandon Tyler Ustaris:
     • #ALUTs = 559, #Registers = 1007, Area = 1566
     • Clock frequency = 325.10 MHz, Clock cycles = 258
     • Delay = 793.60 ns, Area*Delay = 1.243 x 10^-3
  3. Rui Han:
     • #ALUTs = 786, #Registers = 897, Area = 1683
     • Clock frequency = 293.17 MHz, Clock cycles = 249
     • Delay = 849.34 ns, Area*Delay = 1.429 x 10^-3
  Congratulations!!!
  
  

  Please email Prof. Lin if we missed your partner's name or if you think your design should be in the top 3, but is not listed.

• 03-23: For the SHA1 project, the median results are:
  • Delay = 1345.57 ns
  • Area*Delay = 3.114 x 10^-3

• 03-17: The Best Area*Delay RLE designs have been updated. See 03-06 announcement below.

• 03-07: For SHA1_hash_testbench_511.v, here are the intermediate values for W[t], A[t+1], B[t+1], C[t+1], D[t+1], E[t+1], F[t], and K[t] for each time step t.
  
  

  For SHA1_hash_testbench_v6.v, here are the intermediate values for W[t], A[t+1], B[t+1], C[t+1], D[t+1], E[t+1], F[t], and K[t] for each time step t. This is essentially the same as what was posted previously for SHA1_hash_testbench_v6.v, except that the "F[t]" column now represents F at time step t, whereas in what was posted before, the "F" column represented F at time step t+1.

• 03-06: For the RLE project, the top designs for Best Delay are:
  1. Dylan McNamara:
     • #ALUTs = 634, #Registers = 171, Area = 805
     • Clock period = 3.95 ns, Clock cycles = 55
     • Delay = 217 ns, Area*Delay = 1.75 x 10^-4
  2. Yifeng Bu & Jinzhe Zhang:
     • #ALUTs = 595, #Registers = 239, Area = 834
     • Clock period = 4.50 ns, Clock cycles = 49
     • Delay = 220 ns, Area*Delay = 1.84 x 10^-4
  3. John Hwang & Kevin Sam:
     • #ALUTs = 872, #Registers = 248, Area = 1120
     • Clock period = 5.16 ns, Clock cycles = 53
     • Delay = 273 ns, Area*Delay = 3.06 x 10^-4
  The top designs for Best Area*Delay are:
  1. Justin Chang & Allen Zhao:
     • #ALUTs = 191, #Registers = 132, Area = 323
     • Clock period = 3.13 ns, Clock cycles = 153
     • Delay = 479 ns, Area*Delay = 1.55 x 10^-4
  2. Casey Graff & Spencer Wilson:
     • #ALUTs = 151, #Registers = 196, Area = 347
     • Clock period = 2.38 ns, Clock cycles = 201
     • Delay = 478 ns, Area*Delay = 1.66 x 10^-4
  3. Yan Qi:
     • #ALUTs = 141, #Registers = 155, Area = 296
     • Clock period = 3.13 ns, Clock cycles = 181
     • Delay = 566 ns, Area*Delay = 1.68 x 10^-4
  4. Chingheng Hsieh & Xaioxi Liu:
     • #ALUTs = 229, #Registers = 158, Area = 387
     • Clock period = 3.27 ns, Clock cycles = 135
     • Delay = 442 ns, Area*Delay = 1.71 x 10^-4
  Congratulations!!!
  
  Please email Prof. Lin if we missed your partner's name or if you think your design should be in the top 3, but is not listed.

• 03-06: IMPORTANT: The turn-in instructions for the SHA-1 project have been updated.

• 03-02: Here are the turn-in instructions for the SHA-1 project. No need to submit state machine diagrams.

• 03-02: IMPORTANT: Your SHA-1 design must simulate correctly for both SHA1_hash_testbench_v6.v and SHA1_hash_testbench_511.v. You should use the cycle count results from SHA1_hash_testbench_v6.v to evaluate your Delay.

• 03-02: IMPORTANT: Here is the template for your final report. The final report counts 5% towards your grade. For your final report, please submit a PDF file with the file named Lastname1_Lastname2.pdf if you have a team of 2 or Lastname.pdf
  if you did the project alone. You should start on your final report as soon as possible since the background sections can d be written before your project is completed.

• 03-02: For the RLE project, the median results are:
  • Delay = 602.30 ns
  • Area*Delay = 2.61 x 10^-4
  We are still verifying the top designs in delay and in area*delay. We will post them after they have been verified.

• 02-10: IMPORTANT: For both the RLE and SHA1 projects, we will accept designs as passing even if they generate the error message "Error: memory reference not aligned!". Please however limit yourself to reading and writing the memory at word boundaries.

• 02-10: REMINDER: Here are the turn-in instructions for the RLE project. No need to submit state machine diagrams.

• 02-10: IMPORTANT: RLE project due date extended to Sunday, 2/14/2016, 11:59pm PT.

• 02-10: Note that there are several logically equivalent ways to compute F(X, Y, Z). See the Wikipedia page on SHA-1.

• 02-10: For the SHA1 final project, this was the Best Delay result from last year.
  • #ALUTs = 735, #Registers = 981, Area = 1716
  • Clock frequency = 311.53 MHz, Clock cycles = 252
  • Delay = 809 ns, Area*Delay = 1.3881 x 10^-3
  This was the Best Area*Delay result from last year.
  • #ALUTs = 649, #Registers = 938, Area = 1587
  • Clock frequency = 305.06 MHz, Clock cycles = 256
  • Delay = 839 ns, Area*Delay = 1.3318 x 10^-3
  These were the median results from last year.
  • Delay = 1324 ns
  • Area*Delay = 2.75 x 10^-3

• 02-10: IMPORTANT: For the SHA1 project, Altera Quartus will automatically replace some registers with block memories, which are not counted in the total number of registers. If you look at the Analysis & Synthesis Summary, you will see a Total block memory bits entry. If it is non-zero, it means block memories were allocated. To provide a common basis for comparison, you should disable the use of block memories, which can be done as follows (for Quartus II 14.1):
  • From the top menu, go to 'Assignments/Settings/Compiler Settings', and click on 'Advanced Settings (Synthesis)'.
  • Look for "Auto Shift Register Replacement" and double click on the value next to it (by default it is Auto).
  • It will show a drop down menu, make sure to select 'Off'
  • Save your changes by clicking 'OK' on both windows

• 02-10: For SHA1_hash_testbench_v6.v, the intermediate values of (A, B, C, D, E, F) for each time step t are posted here.

• 02-10: For the testbench SHA1_hash_testbench_v6.v, this should be the message text, and this should be the corresponding W arrays. Specifically, the message text of this testbench has 120 bytes = 30 words. There should be three 512-bit blocks after padding, which should corresponding to the three sets of w[0] ... w[15] entries. e.g., for this benchmark, for the first block (Block 0), we should have
  • w[0] = changeEndian(message[0]),
  • w[1] = changeEndian(message[1]),
  • ...
  • w[15] = changeEndian(message[15]).
  The padding of 1 occurs in the second block, and the storage of the message size in bits occurs in the third and final block.

• 02-03: We went over the SHA-1 project today. We will repeat the presentation again next Wednesday 02/10 for those who missed the lecture today.

• 02-03: Here are two papers about FPGA implementations of the SHA-1 algorithm: paper1 and paper2. They are not necessarily the best possible designs, but they will give you some ideas regarding possible optimizations.

• 01-27: "Inferred latches" occurs when there is an incompletely specified "case" or "if-then-else" statement in a function or combinational always statement. This is not allowed in your RLE and SHA1 projects. Here are the slides that discusses about this problem, and the corresponding latch_case_problem.v and latch_if_problem.v examples.

• 01-27: Several sample implementations of the Fibonacci calculator can be found here, including slides on one of the implementations.

• 01-15: Monday 1/18 is Martin Luther King Jr. holiday, so there will be no TA office hours on Monday 1/18.

• 01-13: For the RLE and SHA1 project, the memory model in the testbenches assumes the following:
  • "port_A_addr" is the "byte address", not the memory address. However, the memory can only be accessed at word boundary.
  • This means the first memory location is 0, the next memory location is 4, and the next memory location is 8, and so forth.
  • Therefore, your address counter should increment by 4 each time.
  • If you want to increment an address counter by 1 each time (e.g. "addr <= addr + 1"), then you can also just do "port_A_addr <= (addr << 2), which would make it equivalent to incrementing by 4.

• 01-13: There is some confusion about a sentence in the Fibonacci calculator project description. It says Note that your design should be able to process next fibonacci number just by toggling begin_fibo without having to reset the design for each input corresponding to the value of input_s.
  
  This is what it is intended to mean: When reset_n is 0, you should initialize your state register to an idle state (you can name the idle state any name you want, e.g. s0 or IDLE). In the idle state, you should wait in that state until begin_fibo becomes 1, at which point you should store the "n <= input_s" value and compute the corresponding fibonacci number F(n), e.g. "input_s" may be 5, so you'd need to compute F(5). When your design completes the calculation, it should set "done <= 1" and "fibo_out" to the F(n) number. Then, your design should go back to the idle state where it will wait for begin_fibo again to compute another fibonacci number, e.g. "input_s" may be 9, so you'd compute F(9).
  
  Although the testbench will test for F(5), then F(9), then F(12), with increasing "input_s", your design should be able to work if the next Fibonacci calculation has a smaller "input_s".

• 01-13: Here are the turn-in instructions for the Fibonacci calculator project and for the RLE project.

• 01-13: For the testbench rle_testbench.v, the characters in the input text file plaintext.dat and in the output compressed text file are shown in hexidecimal. For example, in the output compressed text file, the count "28" is in hexidecimal, which is equivalent to a decimal count of "40". Similarly, for testbench rle_testbench2.v, the characters in the input text file plaintextLong.dat and the output compressed text are in hexidecimal as well.

• 01-13: This slide shows the correspondence between the plaintext and the compressed text in the rle_testbench.v testbench.

• 01-13: In Quartus, you have to select a directory/folder location for your project. Under the project folder, there should be a folder named "output_files". Under the "output_files" folder, there is a file labeled with a ".flow.rpt" extension that provides a synthesis report, which includes information about the number of ALUTs, number of registers, etc. There is also a file labeled with a ".sta.rpt" extension that provides a static timing analysis report, which includes information about "Fmax".

• 01-11: For both the RLE and SHA1 projects, use the Fmax result from the Slow 900mV 100C Model to report your clock period. (Do not use the Restricted Fmax.)

• 01-11: Passing requirement the RLE project for this quarter (Winter 2016):
  • Your design must have
    • Delay ≤ 825.60 ns
    • Area*Delay ≤ 3.22 x 10^-4

• 01-11: For the RLE project, here are the results from last year (Winter 2015):
  • Best Delay:
    • #ALUTs = 344, #Registers = 310, Area = 654
    • Clock period = 2.45 ns, Clock cycles = 58
    • Delay = 142 ns, Area*Delay = 0.93 x 10^-4
  • Best Area*Delay:
    • #ALUTs = 344, #Registers = 310, Area = 654
    • Clock period = 2.45 ns, Clock cycles = 58
    • Delay = 142 ns, Area*Delay = 0.93 x 10^-4
  • Median result:
    • Area = 443.98
    • Delay = 561.73 ns
    • Area*Delay = 2.35 x 10^-4

• 01-10: TA Office Hours have been moved to EBU1-2315 (not EBU1-4506), and the hours have also slightly changed. Office hours will start Monday 1/11.

• 01-07: A Piazza page has been set up for forum discussions.

• 01-07: TA office hours have been posted. They will start next Monday 1/11.

• 01-05: Please note that Section C00 will be held in EBU1-2315, not EBU1-2321.

• 01-04: Welcome to the first day of class. Part of this class will be on ASIC design using Verilog hardware description language. To get started, please go to the software download page for instructions on how to download the Altera Quartus II Web Edition Verilog compiler, the ModelSim-Altera Starter Edition logic simulator, and the Icarus Verilog simulator (an alternative simulator that just does logic simulation). All are available for free download. You can start trying the Verilog examples in the tutorial page.

• 01-04: No textbook is required for this course. If you'd like a book on Verilog, one suggestion is the following:
  • A Verilog HDL Primer, Third Edition, by J. Bhasker.

• 01-04: Please use the following FPGA for all your projects:
  • Device family: Arria II GX
  • Device name: EP2AGX45DF29I5
  This device is the last device in the select menu for the Arria II GX family. This is the largest FPGA device in this family. We will use this device for reporting area and delay performance.

• 01-04: Altera has a good short Verilog HDL Basics online course. It provides a good introduction. Please review it.

• 01-04: Before next Monday 01-11, you should have the following accomplished:
  • Quartus/Modelsim software installed.
  • Go through the Altera Verilog HDL Basics online course.
  • Go through the demos at Altera's Demonstration Center.
  • Go through our Quartus and Icarus tutorial pages.